The present invention is directed to memory cell assemblies and methods of forming and using the memory cells, and more particularly, to high density memory cell assemblies including a single first electrode and a plurality of second electrodes and methods of forming and using the memory cells.
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such application is for memory cells. A variety of memory cell types have been developed including, for example, random access memory (RAM), read-only memory (ROM), and programmable read-only memory (PROM). ROM and PROM memory cells are typically used to store information that can be accessed quickly, however, programming of PROM memory cells is often much slower than for RAM memory cells.
A variety of PROM memory cells have been developed which allow for reprogramming. Among the most useful are flash memory cells and electrically erasable PROM (EEPROM) cells. The programming of these memory cells can be erased, for example, by sending an electrical signal through the cells. A review of different types and configurations for these memory cells is provided in S. Wolf, Silicon Processing for the VLSI Era, Vol. 2: Processing Integration, pp. 567-638, incorporated herein by reference.
Many memory cells include, as a base component, a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is used as one of the basic building blocks of many modem electronic circuits. Thus, such circuits realize improved performance and lower costs as the performance of the MOS transistor is increased and as the manufacturing costs are reduced.
A typical MOS semiconductor device 50 suitable for a memory cell generally includes a semiconductor substrate 52 on which a gate electrode 54 is disposed, as shown in FIG. 1. The gate electrode 54, which acts as a conductor, receives an input signal to control operation of the device.
Source and drain regions 56 are typically formed in regions of the substrate adjacent the gate electrode by heavily doping these regions with a dopant material of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
A channel region 58 is formed in the semiconductor substrate beneath the gate electrode 54 and between the source and drain regions 56. The channel is often lightly doped with a dopant material having a conductivity type opposite to that of the source and drain regions. The gate electrode is generally separated from the substrate by an insulating layer 60, typically an oxide layer such as SiO2. The insulating layer is provided to restrain current from flowing between the gate electrode 54 and the source, drain or channel regions 56, 58.
MOS devices typically fall in one of two groups depending on the type of dopant materials used to form the source, drain and channel regions. The two groups are often referred to as n-channel and p-channel devices. The type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field. In an n-channel MOS (NMOS) device, for example, the conductivity of the channel under a transverse electric field is of the conductivity type associated with n-type impurities (e.g., arsenic or phosphorous). Conversely, the channel of a p-channel MOS (PMOS) device under the transverse electric field is associated with p-type impurities (e.g., boron).
One type of conventional memory cell is prepared from the MOS device by disposing a second electrode over the gate electrode. The memory cell device is programmed by applying a potential between the gate electrode and the second electrode that transfers holes or electrons from one electrode to the other to define one state (e.g., a xe2x80x9c1xe2x80x9d state). The absence of transferred charge indicates the other state (e.g., a xe2x80x9c0xe2x80x9d state).
There is a desire to decrease the size of electronic components and, in particular, to increase the density of memory cells for a given device size. In part, this is accomplished by decreasing the size of the base MOS device. However, there is a need for the development of other methods for increasing the density of memory cells and for devices with increased memory cell density.
Generally, the present invention relates to semiconductor devices, memory cells, and methods of forming memory cells from semiconductor devices. One embodiment of the invention is a memory cell assembly that includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode from the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode.
Another embodiment is a method of making a memory cell. A first electrode is formed over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.
A further embodiment is a method of making a memory cell. An insulation layer is formed over a portion of a substrate and a first electrode is formed over the insulating layer. A first dielectric layer is formed over the first electrode. Portions of the first dielectric layer are removed to form a plurality of gaps in the first dielectric layer and exposing a plurality of isolated regions of the first electrode, leaving a remaining portion of the first dielectric layer between the plurality of gaps. A second dielectric layer is formed over the plurality of isolated regions of the first electrode. A second electrode layer is formed over the second dielectric layer and within the plurality of gaps. The second electrode layer forms a plurality of second electrodes separated by the remaining portion of the first dielectric layer.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The Figures and the detailed description which follow more particularly exemplify these embodiments.